Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

ABSTRACT

Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods offorming transistors, to semiconductor processing methods of formingdynamic random access memory circuitry, and to related integratedcircuitry.

BACKGROUND OF THE INVENTION

[0002] Semiconductor processing typically involves a number ofcomplicated steps which include patterning, etching, and doping orimplanting steps, to name just a few, which are necessary to formdesired integrated circuitry. One emphasis on improving the methodsthrough which integrated circuitry is formed, and which is directed toreducing the processing complexity, relates to reducing the number ofprocessing steps. By reducing the number of processing steps, risksassociated with processing mistakes entering into the processing floware reduced. Additionally, wherever possible, it is also highlydesirable to reduce processing complexities while providing addedflexibility in the processing itself.

[0003] For example, several processing steps are required to formtransistor constructions. One or more of these steps can include athreshold voltage definition step in which one or more channelimplantation steps are conducted to define the threshold voltage for theultimately formed transistor. In some applications, it is desirable tohave transistors with different threshold voltages. Typically, differentthreshold voltages are provided by additional masking and doping orimplanting steps to adjust the doping concentration within the channelregion of the various transistors desired to have the differentthreshold voltage. Specifically, one transistor might be masked whileanother receives a threshold implant; and then other of the transistorsmight be masked while the first-masked transistor receives a thresholdimplant.

[0004] This invention grew out of concerns associated with reducing theprocessing complexities involved in forming transistors having differentthreshold voltages.

SUMMARY OF THE INVENTION

[0005] Semiconductor processing methods of forming transistors,semiconductor processing methods of forming dynamic random access memorycircuitry, and related integrated circuitry are described. In oneembodiment, active areas are formed over a substrate, with one of theactive areas having a width of less than one micron. A gate line isformed over the active areas to provide transistors having differentthreshold voltages. Preferably, the transistors are provided withdifferent threshold voltages without using a separate channel implantfor the transistors. The transistor with the lower of the thresholdvoltages corresponds to the active area having the width less than onemicron.

[0006] In another embodiment, a plurality of shallow trench isolation(STI) regions are formed within a substrate and define a plurality ofactive areas having widths at least some of which are no greater thanabout one micron, with at least two of the widths preferably beingdifferent. A gate line is formed over the respective active areas toprovide individual transistors, with the transistors corresponding tothe active areas having the different widths having different thresholdvoltages. In an STI process, devices having width smaller than 1 microntypically also have a lower threshold voltage. This is referred to as“reversed narrow width” effect as contrasted with the case oftransistors formed using LOCOS isolation, where threshold voltage tendsto increase as device width decreases.

[0007] In another embodiment, two field effect transistors arefabricated having different threshold voltages without using a separatechannel implant for one of the transistors versus the other.

[0008] In yet another embodiment, two series of field effect transistorsare formed, with one series being isolated from adjacent devices byshallow trench isolation, the other series having active area widthsgreater than one micron. The one series is formed to have active areawidths less than one micron to achieve lower threshold voltages than theother of the series.

[0009] In yet another embodiment, one of the two series of field effecttransistors are isolated by shallow trench isolation, and differentthreshold voltages between the field effect transistors in differentseries are achieved by varying the active area widths of the fieldeffect transistors in the series. At least one of the series preferablyhas active area widths less than one micron.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0011]FIG. 1 is a diagrammatic side sectional view of the semiconductorwafer fragment in process in accordance with one embodiment of theinvention.

[0012]FIG. 2 is a view of the FIG. 1 wafer fragment at a processing stepwhich is subsequent to that which is shown in FIG. 1.

[0013]FIG. 3 is a plan view of the FIG. 1 wafer fragment at a processingstep which is subsequent to that which is shown in FIG. 2.

[0014]FIG. 4 is a side view of the FIG. 3 wafer fragment.

[0015]FIG. 5 is a schematic diagram of circuitry formed in accordancewith another embodiment of the invention.

[0016]FIG. 6 is a schematic diagram of circuitry formed in accordancewith another embodiment of the invention.

[0017]FIG. 7 is a schematic diagram of circuitry formed in accordancewith another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0019] Referring to FIG. 1, a semiconductor wafer fragment in process isshown generally at 10, and includes a semiconductive substrate 12. Inthe context of this document, the term “semiconductive substrate” isdefined to mean any construction comprising semiconductive material,including, but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0020] Referring to FIG. 2, a plurality of active areas are formed oversubstrate 12, with an exemplary pair of active areas 14, 16 being shown.Active areas 14, 16 can constitute individual active sub-areas within alarger active area. In a preferred embodiment, active areas or sub-areas14, 16 are defined between a plurality of shallow trench isolationregions 18 which are received within substrate 12. The spacing ofshallow trench isolation regions 18 defines a plurality of active areawidths, with exemplary widths being shown at w₁, and w₂. Preferably, atleast two of the widths are different from one another. Of course, morethan two of the widths could be different from one another.

[0021] In one embodiment, some of the active area widths are no greaterthan about one micron. One micron happens to be a break point that istechnologically dependent. In other words, STI transistors show athreshold voltage reduction with reducing gate width when the gate widthis about one micron or less. It will be understood that other sizes thatcorrespond to a break point in threshold voltage versus gate width orcontrol element size for transistors made using other technologies couldbe used instead of “one micron”.

[0022] In one embodiment, one or both of widths w₁ and w₂ could be lessthan one micron. In a preferred embodiment, the different active areawidths impart to transistors which are to be formed, different thresholdvoltages which, in a most preferred embodiment, are achieved withoutconducting or using a separate channel implant for the differenttransistors. Such results in a reduction in the number of processingsteps which were previously required to form transistors havingdifferent threshold voltages.

[0023] In one embodiment, the different threshold voltages are each lessthan two volts. In another embodiment, the different threshold voltagesare each less than one volt. In this example, the transistor having thelower of the threshold voltages corresponds to the transistor which isformed relative to the active area having the lesser or smaller activearea width.

[0024] With respect to provision of the channel implant(s) which definesthe threshold voltages, one or more such implants can be conductedrelative to the active areas. Preferably, each of the one or morechannel implants are common to the transistors having the differentactive area widths which, in turn, provides transistors having differentthreshold voltages.

[0025]FIG. 3 is a plan view of the FIG. 1 wafer fragment at a processingstep which is subsequent to that which is shown in FIG. 2, and FIG. 4 isa side view of the FIG. 3 wafer fragment. A transistor gate line 20 isformed over respective active areas 14, 16 to provide individualtransistors, wherein the transistors corresponding to the active areashaving the different active area widths have different thresholdvoltages as discussed above. Gate lines such as line 20 typically have agate oxide layer, one or more conductive layers such as polysilicon anda silicide layer, one or more insulative caps, and insulative sidewallspacers (not shown), none of which are specifically designated. Theillustrated gate line constitutes a common gate line which is formedover the illustrated active areas. It is, of course, possible to formseparate gate lines over the active areas having the different widths.

[0026] Alternately considered, and in accordance with one embodiment ofthe present invention, two series of field effect transistors are formedover substrate 12. One of the series of field effect transistors (anexemplary transistor of which being formed over active area 14) isisolated from other adjacent devices by shallow trench isolation regions18. The other series of field effect transistors (an exemplarytransistor of which being formed over active area 16) has active areawidths greater than one micron, with the first-mentioned series beingformed to have active area widths less than one micron to achieve lowerthreshold voltages than the other of the series. Preferably, thethreshold voltages for the two series of field effect transistors aredefined by one or more common channel implants. In a most preferredembodiment, the one or more common channel implants are the onlyimplants which define the threshold voltages for the two series of fieldeffect transistors.

[0027] Further and alternately considered, and in accordance withanother embodiment of the present invention, the two series of fieldeffect transistors just mentioned include at least one series which isisolated from adjacent devices by shallow trench isolation regions suchas regions 18. Different threshold voltages are achieved between fieldeffect transistors in the different series by varying the active areawidths of the field effect transistors in the series, with at least oneof the series having active area widths less than one micron, or lessfor future technologies.

[0028] Accordingly, field effect transistors can be fabricated havingdifferent threshold voltages without using a separate channel implantfor the field effect transistors having the different thresholdvoltages. Such can result in a reduction in processing steps, whichformerly included additional masking steps. One or more of the activeareas can have widths less than one micron, with such widths beingvaried in order to change the threshold voltages of the transistorsformed thereover.

[0029] In operation, various methods of the invention provide integratedcircuitry having transistors with different threshold voltages withoutthe added processing complexity. In a preferred embodiment, variousmethods of the invention can provide dynamic random access memorycircuitry having a memory array area for supporting memory circuitry anda peripheral area for supporting peripheral circuitry. A plurality ofshallow trench isolation regions are received within the peripheral areaof the substrate and define a plurality of active areas having widthswithin the substrate, some of the widths being no greater than about onemicron. Preferably, at least two of the widths are different. Aconductive line is formed or disposed over the respective active areasto provide MOS gate electrodes for individual transistors. Thetransistors corresponding to the active areas having the differentwidths preferably have different threshold voltages. Exemplary dynamicrandom access memory circuitry is described in U.S. Pat. Nos. 5,702,990and 5,686,747, which are incorporated by reference.

[0030] Referring to FIG. 5, a circuit 28 is provided and includestransistors 30, 32. Such transistors can be fabricated, in accordancewith the methods described above, to have different threshold voltages.In this example, transistor 30 serves as a pass transistor and has a lowthreshold voltage V_(t1), while transistor 32 serves as a switchingtransistor and has a high threshold voltage V_(th).

[0031] Referring to FIG. 6, a circuit 34 is provided and includestransistors 36, 38 which can have different threshold voltages. Suchcircuit comprises a portion of precharge circuitry for dynamic randomaccess memory circuitry. In the example of FIG. 6, the transistor 36 hasa low threshold voltage V_(t1) and the transistor 38 has a highthreshold voltage V_(th).

[0032] Referring to FIG. 7, a circuit is shown generally at 40 andcomprises transistors 42, 44 and 46 having threshold voltages V_(t1),V_(t2) and V_(t3), respectively. The transistors 42, 44 and 46 arefabricated to be formed in a parallel configuration with a common gateline 48 interconnecting the transistors 42, 44 and 46 and coupling asignal CSAL to gates of the transistors. In this example, thetransistors 42, 44, 46 each have different active area widths whichresults in different threshold voltages.

[0033] Also shown in FIG. 7 is a sense amplifier circuit 50 includingcross-coupled transistors 52 and 54. In one embodiment, the transistors52 and 54 are formed to have a low threshold voltage V_(t1). When thesignal C_(SAL) goes to logic “1”, the common node labeled RNL*equilibrates the potentials on sources of the transistors 52 and 54 inpreparation for reading stored data from memory cells in a memory array(not shown). In the example shown in FIG. 7, the circuit 40 acts as apull-down circuit and equilibrates the node RNL* to ground. Use ofmultiple transistors 42, 44 and 46 having different threshold voltagesfacilitates (“softens”) sensing at the beginning of the sensing cycleand also more rapid sensing at the end of the cycle when differentialsignals have been developed by the transistors 52 and 54.

[0034] Advantages of the invention can include provision of a pluralityof transistors having different threshold voltages, without thenecessity of providing different dedicated processing steps to achievesuch different threshold voltages. In various preferred embodiments,such results are attained through the use of shallow trench isolationand various so-called reverse narrow width characteristics.Additionally, current drive can be achieved using multiple narrow widthdevices in parallel (FIG. 7). The invention can be useful for lowthreshold voltage applications such as precharge circuitry in DRAMcircuitry, or as output drivers where low threshold voltages areimportant to obtain higher signal levels.

[0035] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method of forming transistors comprising:forming a plurality of shallow trench isolation regions received withina substrate, the shallow trench isolation regions being formed to definea plurality of active areas having widths within the substrate, some ofthe widths being no greater than about one micron, at least two of thewidths being different; and forming a gate line over respective activeareas to provide individual transistors, the transistors correspondingto the active areas having the different widths having differentthreshold voltages.
 2. The semiconductor processing method of claim 1further comprising for the transistors having the different widths,providing the different threshold voltages without using a separatechannel implant for the transistors.
 3. The semiconductor processingmethod of claim 1, wherein the two different widths are each less thanone micron.
 4. The semiconductor processing method of claim 1, whereinthe different threshold voltages are each less than 2 volts.
 5. Thesemiconductor processing method of claim 1, wherein the differentthreshold voltages are each less than 1 volt.
 6. The semiconductorprocessing method of claim 1, wherein the two different widths are eachless than one micron, and the different threshold voltages are each lessthan 2 volts.
 7. The semiconductor processing method of claim 1, whereinthe two different widths are each less than one micron, and thedifferent threshold voltages are each less than 1 volt.
 8. A method offorming a pair of field effect transistors comprising: forming a pair ofactive areas over a substrate, one of the active areas having a widthless than one micron; forming a gate line over both active areas toprovide a pair of transistors having different threshold voltages, thetransistors being provided with the different threshold voltages withoutusing a separate channel implant for either transistor; and wherein thetransistor with the lower of the threshold voltages corresponds to theactive area having the width less than one micron.
 9. The method ofclaim 8 further comprising forming the transistor having the higher ofthe threshold voltages to have an active area width greater than onemicron.
 10. The method of claim 8 further comprising forming thetransistor having the higher of the threshold voltages to have an activearea width less than one micron.
 11. The method of claim 8 furthercomprising conducting only one common channel implant for the pair oftransistors.
 12. The method of claim 8, wherein the forming of the pairof active areas comprises forming shallow trench isolation regionsreceived within the substrate proximate the active areas.
 13. The methodof claim 8, wherein the forming of the gate line comprises forming acommon gate line over the active areas.
 14. The method of claim 8,wherein the forming of the gate line comprises forming a common gateline over the active areas, the transistors being formed in a parallelconfiguration.
 15. A method of forming integrated circuitry comprisingfabricating two field effect transistors having different thresholdvoltages without using a separate channel implant for one of thetransistors versus the other.
 16. The method of claim 15, wherein thefabricating of the two field effect transistors comprises forming atleast one active area of one of the transistors to have a width lessthan one micron.
 17. The method of claim 15, wherein the fabricating ofthe two field effect transistors comprises forming both active areas ofthe transistors to have widths less than one micron.
 18. The method ofclaim 15, wherein the fabricating of the two field effect transistorscomprises forming both active areas of the transistors to have differentwidths.
 19. The method of claim 15, wherein the fabricating of the twofield effect transistors comprises forming both active areas of thetransistors to have different widths, each of which being less than onemicron.
 20. The method of claim 15, wherein the fabricating of the twofield effect transistors comprises forming shallow trench isolationregions within a substrate proximate the two field effect transistors,the shallow trench isolation regions defining, at least in part, activearea widths of the transistors.
 21. A semiconductor processing methodcomprising forming two series of field effect transistors over asubstrate, one series being isolated from adjacent devices by shallowtrench isolation, the other series having active area widths greaterthan one micron, the one series being formed to have active area widthsless than one micron to achieve lower threshold voltages than the otherof the series.
 22. The semiconductor processing method of claim 21,wherein the threshold voltages for the two series of field effecttransistors are defined by a common channel implant.
 23. Thesemiconductor processing method of claim 21, wherein the thresholdvoltages for the two series of field effect transistors are defined by acommon channel implant, said implant being the only channel implantwhich defines the threshold voltages for the two series of field effecttransistors.
 24. The semiconductor processing method of claim 21,wherein the threshold voltages for the two series of field effecttransistors are defined by one or more common channel implants.
 25. Thesemiconductor processing method of claim 21, wherein the thresholdvoltages for the two series of field effect transistors are defined byone or more common channel implants, said common channel implants beingthe only channel implants which define the threshold voltages for thetwo series of field effect transistors.
 26. A semiconductor processingmethod comprising forming two series of field effect transistors over asubstrate, at least one series being isolated from adjacent devices byshallow trench isolation, and further comprising achieving differentthreshold voltages between field effect transistors in different seriesby varying the active area widths of the field effect transistors in theseries, at least one series having active area widths less than onemicron.
 27. The semiconductor processing method of claim 26, wherein thethreshold voltages for the two series of field effect transistors aredefined by a common channel implant.
 28. The semiconductor processingmethod of claim 26, wherein the threshold voltages for the two series offield effect transistors are defined by a common channel implant, saidimplant being the only channel implant which defines the thresholdvoltages for the two series of field effect transistors.
 29. Thesemiconductor processing method of claim 26, wherein the thresholdvoltages for the two series of field effect transistors are defined byone or more common channel implants.
 30. The semiconductor processingmethod of claim 26, wherein the threshold voltages for the two series offield effect transistors are defined by one or more common channelimplants, said common channel implants being the only channel implantswhich define the threshold voltages for the two series of field effecttransistors.
 31. A semiconductor processing method of forming dynamicrandom access memory circuitry comprising: providing a substrate havinga memory array area over which memory circuitry is to be formed, and aperipheral area over which peripheral circuitry is to be formed; forminga plurality of shallow trench isolation regions received within theperipheral area of the substrate, the shallow trench isolation regionsbeing formed to define a plurality of active areas having widths withinthe substrate, some of the widths being no greater than about onemicron, at least two of the widths being different; and forming aconductive line over respective active areas to provide individualtransistor gates, the transistors corresponding to the active areashaving the different widths having different threshold voltages.
 32. Thesemiconductor processing method of claim 31 further comprising for thetransistors having the different widths, providing the differentthreshold voltages without using a separate channel implant for thetransistors.
 33. The semiconductor processing method of claim 31,wherein the two different widths are each less than one micron.
 34. Atransistor assembly comprising: a plurality of active areas havingwidths defined by shallow trench isolation regions of no greater thanabout one micron, at least some of the widths being different; and gatelines disposed over the plurality of active areas to provide individualtransistors, those transistors whose widths are different havingdifferent threshold voltages from one another.
 35. The transistorassembly of claim 34, wherein the threshold voltages of at least some ofthe individual transistors are less than one volt.
 36. The transistorassembly of claim 34, wherein individual transistors having active areaswith the smaller widths have threshold voltages which are smaller thanother individual transistors having active areas with larger widths. 37.The transistor assembly of claim 34, wherein one of the transistorscomprises a portion of precharge circuitry for dynamic random accessmemory circuitry.
 38. The transistor assembly of claim 34, wherein oneof the transistors comprises a pass transistor.
 39. The transistorassembly of claim 34, wherein one of the transistors comprises a portionof sense amplifier circuitry for dynamic random access memory circuitryand has a lower threshold voltage V_(t1).
 40. The transistor assembly ofclaim 34, wherein some of the transistors are joined together in aparallel configuration.
 41. Dynamic random access memory circuitrycomprising: a substrate having a memory array area for supporting memorycircuitry and a peripheral area for supporting peripheral circuitry; aplurality of active areas within the peripheral area having widthsdefined by shallow trench isolation regions of no greater than about onemicron, at least some of the widths being different; and conductivelines disposed over the plurality of active areas to provide individualtransistors, those transistors whose widths are different havingdifferent threshold voltages from one another.
 42. The dynamic randomaccess memory circuitry of claim 41, wherein the threshold voltages ofat least some of the individual transistors are less than one volt. 43.The dynamic random access memory circuitry of claim 41, whereinindividual transistors having active areas with the smaller widths havethreshold voltages which are smaller than other individual transistorshaving active areas with larger widths.
 44. A transistor assemblycomprising: an active area; a plurality of spaced-apart shallow trenchisolation regions received by the active area and defining activesub-areas therebetween, individual active sub-areas having respectivewidths, at least one of the widths being no greater than about onemicron and at least one other sub-area having a width which is differentfrom the one width; and a gate line extending over the one and the othersub-area and defining, in part, separate transistors, wherein theseparate transistors have different threshold voltages.
 45. Thetransistor assembly of claim 44, further comprising a gate lineextending over a plurality of the active sub-areas defining a pluralityof transistors, each active sub-area width of an associated transistorbeing no greater than about one micron.
 46. The transistor assembly ofclaim 44, further comprising a gate line extending over a plurality ofthe active sub-areas defining a plurality of transistors, each activesub-area width of an associated transistor being no greater than aboutone micron, wherein more than two of the plurality of transistors havedifferent threshold voltages.
 47. The transistor assembly of claim 44,wherein said gate line comprises a common gate line which extends over aplurality of the active sub-areas defining a plurality of transistors,each active sub-area width of an associated transistor being no greaterthan about one micron.
 48. The transistor assembly of claim 44, whereinsaid gate line comprises a common gate line which extends over aplurality of the active sub-areas defining a plurality of transistors,each active sub-area width of an associated transistor being no greaterthan about one micron and said plurality of transistors being joined ina parallel configuration.
 49. A transistor assembly comprising: anactive area; a plurality of spaced-apart shallow trench isolationregions received by the active area and defining active sub-areastherebetween, individual active sub-areas having respective widths, atleast one of the widths being no greater than about one micron and atleast one other sub-area having a width which is less than the onewidth; and a gate line extending over the one and the other sub-area anddefining, in part, separate transistors, wherein the separatetransistors have different threshold voltages, wherein said gate linecomprises a common gate line which extends over a plurality of theactive sub-areas defining a plurality of transistors, each activesub-area width of an associated transistor being no greater than aboutone micron and said plurality of transistors being joined in a parallelconfiguration to provide a pull down circuit coupled to a common node.50. The transistor assembly of claim 49, further comprising a senseamplifier formed from pair of transistors, each of the pair having agate that is cross-coupled to a drain of another of the pair, sources ofthe pair being coupled to the common node.